1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to a system and method for testing a memory instance at speed.
2. Description of Related Art
Typically, memories are tested and repaired by serially transmitting commands from a built-in self-test and repair (BISTR) interface that is clocked with a test clock and then allowing the memory to perform a read or write operation. A processor, called a BISTR processor, is usually provided for effectuating the testing operations. When several memory instances are interfaced with a single BISTR processor, the serial command transfer process is slow and significantly limited by the delays inherent in the long signal paths necessitated by design and layout constraints. Accordingly, the memory testing operations are executed at a slower frequency than the clock frequency associated with the memory. Additionally, the BISTR processor has to take a finite number of test clock cycles for each operation in order to send all commands serially, thereby substantially impacting the testing performance.